add specs and dev log

.vscode/settings.json

@@ -1,7 +1,12 @@
 {
+<<<<<<< HEAD
     "rust-analyzer.cargo.allTargets": false,
     "rust-analyzer.cargo.extraArgs": [
         "--target",
         "riscv64gc-unknown-none-elf"
     ]
-}
+}
+=======
+	"rust-analyzer.cargo.allTargets": false
+}
+>>>>>>> 85bbe77 (add specs and dev log)

.vscode/tasks.json

@@ -0,0 +1,13 @@
+{
+	"version": "2.0.0",
+	"tasks": [
+		{
+			"type": "process",
+			"command": ["${workspaceFolder}/scripts/start.sh"],
+			"args": [
+				"${workspaceFolder}/target/riscv64gc-unknown-none-elf/debug/kernel"
+			],
+			"label": "run kernel"
+		}
+	]
+}

Cargo.lock

@@ -13,11 +13,16 @@ dependencies = [
  "syn",
 ]
 
+[[package]]
+name = "ir"
+version = "0.1.0"
+
 [[package]]
 name = "kernel"
 version = "0.1.0"
 dependencies = [
  "contracts",
+ "ir",
 ]
 
 [[package]]

Cargo.toml

@@ -3,6 +3,9 @@ name = "kernel"
 version = "0.1.0"
 edition = "2021"
 
+[workspace]
+members = ["crates/*"]
+
 [profile.dev]
 panic = "abort"
 
@@ -11,5 +14,4 @@ panic = "abort"
 
 [dependencies]
 contracts = "0.6.3"
-
-[features]
+ir = { path = "crates/ir" }

crates/ir/.gitignore

@@ -0,0 +1 @@
+/target

crates/ir/Cargo.toml

@@ -0,0 +1,6 @@
+[package]
+name = "ir"
+version = "0.1.0"
+edition = "2021"
+
+[dependencies]

crates/ir/src/lib.rs

@@ -0,0 +1,13 @@
+#![no_std]
+
+pub struct Module {}
+
+pub struct Function {}
+
+pub struct BasicBlock {}
+
+pub enum Instruction {
+  Arithmetic(Arithmetic),
+}
+
+pub enum Arithmetic {}

development.md

@@ -0,0 +1,25 @@
+# Development Log
+
+### 2024-12-16
+
+- Timer reference: https://popovicu.com/posts/risc-v-interrupts-with-timer-example/
+- Another great general OS reference for RISC-V: https://osblog.stephenmarz.com/
+- Looks like OpenSBI abstracts away UART and some other things, and has a bunch of extensions for managing the hardware. One thing you can do with this is create interrupts. I'm going to try to do this.
+- The goal of setting up the interrupts is to go for a green-thread architecture.
+
+### 2024-12-06
+
+- I want to set up some kind of timer-based multitasking.
+- https://github.com/marf/xv6-scheduling
+
+### 2024-12-05
+
+- Linker script annoying bug that didn't put .text at the exact address specified. It kept putting .rodata.\* first, so I just added an explicit entry for that to put it later
+- The way the OS communicates with the QEMU terminal using UART
+
+### 2024-12-04
+
+- QEMU can automatically create a FAT filesystem on the fly https://qemu-project.gitlab.io/qemu/system/qemu-block-drivers.html#virtual-fat-disk-images
+- https://www.qemu.org/2020/07/03/anatomy-of-a-boot/
+- https://xiayingp.gitbook.io/build_a_os Learning resource
+- Rust version of xv6: https://github.com/Jaic1/xv6-riscv-rust

rustfmt.toml

@@ -0,0 +1,2 @@
+tab_spaces = 2
+max_width = 80

scripts/start.sh

@@ -5,6 +5,8 @@ set -x
 KERNEL=$1
 shift
 
+cargo build
+
 qemu-system-riscv64 \
     -nographic \
     -machine virt \

src/main.rs

@@ -2,6 +2,7 @@
 #![no_main]
 
 mod riscv;
+mod sbi;
 mod timer;
 
 use core::{arch::global_asm, panic::PanicInfo, ptr};
@@ -12,7 +13,7 @@ global_asm!(include_str!("asm/entry.S"));
 
 #[panic_handler]
 fn panic_handler(_: &PanicInfo) -> ! {
-    loop {}
+  loop {}
 }
 
 const UART0: usize = 0x10000000;
@@ -20,13 +21,11 @@ static HELLO: &[u8] = b"meow\n";
 
 #[no_mangle]
 pub unsafe extern "C" fn start() -> ! {
-    timer_init();
+  timer_init();
+  for c in HELLO.iter() {
+    while ptr::read_volatile((UART0 + 5) as *const u8) & (1 << 5) == 0 {}
+    ptr::write_volatile((UART0 + 0) as *mut u8, *c);
+  }
 
-    for c in HELLO.iter() {
-        while ptr::read_volatile((UART0 + 5) as *const u8) & (1 << 5) == 0 {}
-
-        ptr::write_volatile((UART0 + 0) as *mut u8, *c);
-    }
-
-    loop {}
+  loop {}
 }

src/sbi.rs

@@ -0,0 +1,12 @@
+//! SBI -- Supervisor Binary Interface
+//!
+//! Docs: https://github.com/riscv-non-isa/riscv-sbi-doc
+//!
+//! QEMU implements this interface.
+
+// https://github.com/popovicu/risc-v-sbi-timer/blob/main/timer.c
+
+use core::arch::asm;
+
+// Implementation from https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
+fn enter_supervisor_mode() {}