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Connecting: ditch head and tail
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Adam Chlipala
parent
daebf21dc0
commit
51a1b7c445
1 changed files with 11 additions and 98 deletions
109
Connecting.v
109
Connecting.v
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@ -964,15 +964,13 @@ Module DeeplyEmbedded(Import BW : BIT_WIDTH).
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| Var (x : var)
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| Const (n : wrd)
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| Add (e1 e2 : exp)
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| Head (e : exp)
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| Tail (e : exp)
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| Read (e : exp)
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| NotNull (e : exp).
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Inductive stmt :=
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| Skip
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| Assign (x : var) (e : exp)
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| WriteHead (x : var) (e : exp)
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| WriteTail (x : var) (e : exp)
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| Write (x : var) (e : exp)
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| Seq (s1 s2 : stmt)
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| IfThenElse (e : exp) (s1 s2 : stmt)
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| WhileLoop (e : exp) (s1 : stmt).
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@ -985,81 +983,6 @@ Module DeeplyEmbedded(Import BW : BIT_WIDTH).
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decide equality.
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Defined.
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Record function := {
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Params : list (var * type);
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Locals : list (var * type);
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Return : type;
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Body : stmt
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}.
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Section fn.
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Variable fn : function.
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Definition vars := Params fn ++ Locals fn ++ [("result", Return fn)].
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Fixpoint varType (x : var) (vs : list (var * type)) : option type :=
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match vs with
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| nil => None
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| (y, t) :: vs' => if y ==v x then Some t else varType x vs'
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end.
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Fixpoint expType (e : exp) : option type :=
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match e with
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| Var x => varType x vars
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| Const _ => Some Scalar
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| Add e1 e2 => match expType e1, expType e2 with
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| Some Scalar, Some Scalar => Some Scalar
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| _, _ => None
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end
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| Head x => match expType x with
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| Some (ListPointer t) => Some t
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| _ => None
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end
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| Tail x => match expType x with
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| Some (ListPointer t) => Some (ListPointer t)
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| _ => None
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end
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| NotNull e1 => match expType e1 with
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| Some (ListPointer _) => Some Scalar
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| _ => None
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end
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end.
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Fixpoint stmtWf (s : stmt) : bool :=
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match s with
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| Skip => true
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| Assign x e => match varType x vars, expType e with
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| Some t1, Some t2 =>
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if type_eq t1 t2 then true else false
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| _, _ => false
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end
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| WriteHead x e => match varType x vars, expType e with
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| Some (ListPointer t1), Some t2 =>
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if type_eq t1 t2 then true else false
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| _, _ => false
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end
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| WriteTail x e => match varType x vars, expType e with
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| Some (ListPointer t1), Some (ListPointer t2) =>
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if type_eq t1 t2 then true else false
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| _, _ => false
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end
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| Seq s1 s2 => stmtWf s1 && stmtWf s2
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| IfThenElse e s1 s2 => match expType e with
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| Some Scalar => stmtWf s1 && stmtWf s2
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| _ => false
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end
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| WhileLoop e s1 => match expType e with
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| Some Scalar => stmtWf s1
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| _ => false
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end
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end.
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Record functionWf : Prop := {
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VarsOk : NoDup (map fst (Params fn ++ Locals fn));
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BodyOk : stmtWf (Body fn) = true
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}.
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End fn.
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Definition heap := fmap wrd wrd.
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Definition valuation := fmap var wrd.
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@ -1073,14 +996,10 @@ Module DeeplyEmbedded(Import BW : BIT_WIDTH).
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eval H V e1 n1
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-> eval H V e2 n2
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-> eval H V (Add e1 e2) (n1 ^+ n2)
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| VHead : forall H V e1 p ph,
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| VRead : forall H V e1 p v,
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eval H V e1 p
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-> H $? p = Some ph
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-> eval H V (Head e1) ph
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| VTail : forall H V e1 p pt,
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eval H V e1 p
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-> H $? (p ^+ ^1) = Some pt
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-> eval H V (Tail e1) pt
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-> H $? p = Some v
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-> eval H V (Read e1) v
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| VNotNull : forall H V e1 p,
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eval H V e1 p
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-> eval H V (NotNull e1) (if weq p (^0) then ^1 else ^0).
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@ -1089,16 +1008,11 @@ Module DeeplyEmbedded(Import BW : BIT_WIDTH).
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| StAssign : forall H V x e v,
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eval H V e v
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-> step (H, V, Assign x e) (H, V $+ (x, v), Skip)
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| StWriteHead : forall H V x e a v hv,
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| StWrite : forall H V x e a v hv,
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V $? x = Some a
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-> eval H V e v
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-> H $? a = Some hv
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-> step (H, V, WriteHead x e) (H $+ (a, v), V, Skip)
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| StWriteTail : forall H V x e a v tv,
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V $? x = Some a
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-> eval H V e v
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-> H $? a = Some tv
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-> step (H, V, WriteTail x e) (H $+ (a, v), V, Skip)
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-> step (H, V, Write x e) (H $+ (a, v), V, Skip)
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| StSeq1 : forall H V s2,
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step (H, V, Seq Skip s2) (H, V, s2)
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| StSeq2 : forall H V s1 s2 H' V' s1',
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@ -1147,8 +1061,7 @@ Module MixedToDeep(Import BW : BIT_WIDTH).
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match s with
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| Assign y _ => if x ==v y then true else false
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| Skip
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| WriteHead _ _
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| WriteTail _ _ => false
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| DE.Write _ _ => false
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| Seq s1 s2
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| IfThenElse _ s1 s2 => couldWrite x s1 || couldWrite x s2
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| WhileLoop _ s1 => couldWrite x s1
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@ -1175,10 +1088,10 @@ Module MixedToDeep(Import BW : BIT_WIDTH).
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V $? x = Some v
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-> translate translate_return V (c v) s1
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-> translate translate_return V (Bind (Return v) c) (Seq Skip s1)
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| TrReadHead : forall V B (a : wrd) (c : wrd -> cmd B) e x s1,
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| TrRead : forall V B (a : wrd) (c : wrd -> cmd B) e x s1,
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translate_exp V a e
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-> (forall w, translate translate_return (V $+ (x, w)) (c w) s1)
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-> translate translate_return V (Bind (Read a) c) (Seq (Assign x (Head e)) s1).
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-> translate translate_return V (Bind (Read a) c) (Seq (Assign x (DE.Read e)) s1).
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Ltac freshFor vm k :=
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let rec keepTrying x :=
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@ -1202,7 +1115,7 @@ Module MixedToDeep(Import BW : BIT_WIDTH).
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eapply TrAssign with (x := y); [ | intro ])
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| [ |- translate _ ?V (Bind (Read _) _) _ ] =>
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freshFor V ltac:(fun y =>
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eapply TrReadHead with (x := y); [ | intro ])
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eapply TrRead with (x := y); [ | intro ])
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end.
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Example adder (a b c : wrd) :=
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