250 lines
7.7 KiB
HCL
250 lines
7.7 KiB
HCL
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## Michael Zhang <zhan4854@umn.edu>
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# H o w i t w o r k s.jpg
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# ----------+-------------------------+
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# Stage | iaddq V, rB |
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# ----------+-------------------------+
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# Fetch | icode:ifun <= M1[PC] |
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# | rA:rB <= M1[PC+1] |
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# | valC <= M8[PC+2] |
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# | valP <= PC+10 |
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# ----------+-------------------------+
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# Decode | valB <= R[rB] |
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# ----------+-------------------------+
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# Execute | valE <= valB+valC |
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# ----------+-------------------------+
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# Memory | n o t h i n g |
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# ----------+-------------------------+
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# WriteBack | R[rB] <= valE |
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# ----------+-------------------------+
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# PCUpdate | PC <= valP |
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# ----------+-------------------------+
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#/* $begin seq-all-hcl */
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####################################################################
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# HCL Description of Control for Single Cycle Y86-64 Processor SEQ #
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# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010 #
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####################################################################
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## Your task is to implement the iaddq instruction
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## The file contains a declaration of the icodes
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## for iaddq (IIADDQ)
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## Your job is to add the rest of the logic to make it work
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####################################################################
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# C Include's. Don't alter these #
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####################################################################
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quote '#include <stdio.h>'
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quote '#include "isa.h"'
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quote '#include "sim.h"'
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quote 'int sim_main(int argc, char *argv[]);'
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quote 'word_t gen_pc(){return 0;}'
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quote 'int main(int argc, char *argv[])'
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quote ' {plusmode=0;return sim_main(argc,argv);}'
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####################################################################
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# Declarations. Do not change/remove/delete any of these #
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####################################################################
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##### Symbolic representation of Y86-64 Instruction Codes #############
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wordsig INOP 'I_NOP'
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wordsig IHALT 'I_HALT'
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wordsig IRRMOVQ 'I_RRMOVQ'
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wordsig IIRMOVQ 'I_IRMOVQ'
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wordsig IRMMOVQ 'I_RMMOVQ'
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wordsig IMRMOVQ 'I_MRMOVQ'
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wordsig IOPQ 'I_ALU'
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wordsig IJXX 'I_JMP'
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wordsig ICALL 'I_CALL'
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wordsig IRET 'I_RET'
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wordsig IPUSHQ 'I_PUSHQ'
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wordsig IPOPQ 'I_POPQ'
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# Instruction code for iaddq instruction
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wordsig IIADDQ 'I_IADDQ'
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##### Symbolic represenations of Y86-64 function codes #####
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wordsig FNONE 'F_NONE' # Default function code
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##### Symbolic representation of Y86-64 Registers referenced explicitly #####
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wordsig RRSP 'REG_RSP' # Stack Pointer
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wordsig RNONE 'REG_NONE' # Special value indicating "no register"
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##### ALU Functions referenced explicitly #####
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wordsig ALUADD 'A_ADD' # ALU should add its arguments
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##### Possible instruction status values #####
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wordsig SAOK 'STAT_AOK' # Normal execution
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wordsig SADR 'STAT_ADR' # Invalid memory address
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wordsig SINS 'STAT_INS' # Invalid instruction
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wordsig SHLT 'STAT_HLT' # Halt instruction encountered
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##### Signals that can be referenced by control logic ####################
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##### Fetch stage inputs #####
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wordsig pc 'pc' # Program counter
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##### Fetch stage computations #####
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wordsig imem_icode 'imem_icode' # icode field from instruction memory
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wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
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wordsig icode 'icode' # Instruction control code
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wordsig ifun 'ifun' # Instruction function
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wordsig rA 'ra' # rA field from instruction
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wordsig rB 'rb' # rB field from instruction
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wordsig valC 'valc' # Constant from instruction
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wordsig valP 'valp' # Address of following instruction
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boolsig imem_error 'imem_error' # Error signal from instruction memory
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boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
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##### Decode stage computations #####
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wordsig valA 'vala' # Value from register A port
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wordsig valB 'valb' # Value from register B port
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##### Execute stage computations #####
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wordsig valE 'vale' # Value computed by ALU
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boolsig Cnd 'cond' # Branch test
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##### Memory stage computations #####
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wordsig valM 'valm' # Value read from memory
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boolsig dmem_error 'dmem_error' # Error signal from data memory
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####################################################################
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# Control Signal Definitions. #
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####################################################################
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################ Fetch Stage ###################################
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# Determine instruction code
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word icode = [
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imem_error: INOP;
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1: imem_icode; # Default: get from instruction memory
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];
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# Determine instruction function
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word ifun = [
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imem_error: FNONE;
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1: imem_ifun; # Default: get from instruction memory
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];
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bool instr_valid = icode in
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{ INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
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IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ };
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# Does fetched instruction require a regid byte?
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bool need_regids =
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icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,
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IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ };
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# Does fetched instruction require a constant word?
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bool need_valC =
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icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL, IIADDQ };
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################ Decode Stage ###################################
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## What register should be used as the A source?
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word srcA = [
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icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;
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icode in { IPOPQ, IRET } : RRSP;
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1 : RNONE; # Don't need register
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];
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## What register should be used as the B source?
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word srcB = [
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icode in { IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : rB;
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icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
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1 : RNONE; # Don't need register
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];
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## What register should be used as the E destination?
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word dstE = [
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icode in { IRRMOVQ } && Cnd : rB;
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icode in { IIRMOVQ, IOPQ, IIADDQ } : rB;
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icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
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1 : RNONE; # Don't write any register
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];
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## What register should be used as the M destination?
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word dstM = [
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icode in { IMRMOVQ, IPOPQ } : rA;
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1 : RNONE; # Don't write any register
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];
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################ Execute Stage ###################################
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## Select input A to ALU
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word aluA = [
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icode in { IRRMOVQ, IOPQ } : valA;
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icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ } : valC;
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icode in { ICALL, IPUSHQ } : -8;
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icode in { IRET, IPOPQ } : 8;
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# Other instructions don't need ALU
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];
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## Select input B to ALU
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word aluB = [
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icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,
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IPUSHQ, IRET, IPOPQ, IIADDQ } : valB;
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icode in { IRRMOVQ, IIRMOVQ } : 0;
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# Other instructions don't need ALU
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];
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## Set the ALU function
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word alufun = [
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icode == IOPQ : ifun;
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1 : ALUADD;
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];
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## Should the condition codes be updated?
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bool set_cc = icode in { IOPQ, IIADDQ };
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################ Memory Stage ###################################
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## Set read control signal
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bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };
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## Set write control signal
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bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };
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## Select memory address
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word mem_addr = [
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icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;
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icode in { IPOPQ, IRET } : valA;
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# Other instructions don't need address
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];
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## Select memory input data
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word mem_data = [
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# Value from register
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icode in { IRMMOVQ, IPUSHQ } : valA;
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# Return PC
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icode == ICALL : valP;
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# Default: Don't write anything
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];
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## Determine instruction status
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word Stat = [
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imem_error || dmem_error : SADR;
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!instr_valid: SINS;
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icode == IHALT : SHLT;
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1 : SAOK;
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];
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################ Program Counter Update ############################
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## What address should instruction be fetched at
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word new_pc = [
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# Call. Use instruction constant
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icode == ICALL : valC;
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# Taken branch. Use instruction constant
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icode == IJXX && Cnd : valC;
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# Completion of RET instruction. Use value from stack
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icode == IRET : valM;
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# Default: Use incremented PC
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1 : valP;
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];
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#/* $end seq-all-hcl */
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